1. Technical Field
This disclosure relates to electronic design automation (EDA). More specifically, this disclosure relates to progressive circuit evaluation for circuit optimization.
2. Related Art
Circuit optimization can be performed during logic synthesis and/or physical synthesis. Some circuit optimization techniques iteratively replace a gate in the circuit design with other gates from a library of gates. Each time the iterative circuit optimization technique replaces a gate with another gate, some optimization techniques perform a timing update of the entire design to check whether or not replacing the gate improved the circuit design.
Updating timing information (e.g., updating arrival and required times) for the entire circuit is computationally expensive (the worst-case complexity of a full timing update can be exponential with respect to the circuit design's size). As a result, the timing update operation often becomes a runtime bottleneck in circuit optimization. It is desirable to improve performance of circuit optimization.